Fin metal-oxide-semiconductor field effect transistor (FinMOSFET) is an emerging technology which provides solutions to metal-oxide-semiconductor field effect transistor (MOSFET) scaling problems at, and below, the 45 nm node. FinMOSFET structures include fin field effect transistors (finFETs), which comprise at least one narrow (preferably <10 nm wide) semiconductor fin gated on at least two opposing sides of each of the at least one semiconductor fin. Preferred prior art finFET structures are formed on a semiconductor-on-insulator (SOI) substrate, because of low source/drain diffusion to substrate capacitance and ease of electrical isolation by shallow trench isolation structures.
However, finFETs fabricated on a SOI substrate suffer from floating body effects, as is well known for conventional planar MOSFETs. The body of a finFET on an SOI substrate stores charge which is a function of the history of the device, hence becoming a “floating” body. As such, floating body finFETs experience threshold voltages which are difficult to anticipate and control, and which vary in time. The body charge storage effects result in dynamic sub-threshold voltage (sub-Vt) leakage and threshold voltage (Vt) mismatch among geometrically identical adjacent devices. Floating body effects in finFETs are particularly a concern in static random access memory (SRAM) cells, where Vt matching is extremely important as operating voltages continue to be scaled down. The floating body also poses leakage problems for pass gate devices. Still another concern with floating body finFETs is with stacked devices, as used in logic gates, in which the conductive state of devices higher up in the stack are strongly influenced by stored body charge, because of reduced gate-to-source voltage (Vgs) overdrive available to these devices. In view of the above stated problems with finFETs fabricated on SOI substrates, it is desirable to eliminate floating body effects by building finFETs incorporating body contacts.
The challenge in forming a body-contacted finFET is to do so without degrading its positive attributes, such as high immunity to short channel effects, steep sub-Vt slope, and high current drive capability due to volume inversion. Although several prior art contacted body finFETs have been identified, all fail to preserve the desirable attributes of the device.
For example, U.S. Patent Application Publication No. 2006/0091463 provides an elongated widened portion of a semiconductor fin between source-drain regions formed in adjacent narrow fin regions. The widened portion of the fin is contacted from above. The presence of the widened portion of the fin in the channel current path seriously degrades the desirable attributes of the finFET. In addition to loss of short channel Vt control, the widened fin portion has a different threshold voltage and channel conductance, which would degrade the channel current. The channel length needs to be much greater than a lithographically printable minimum dimension to avoid body contact to diffusion shorts.
U.S. Pat. No. 6,913,960 discloses another body contacted finFET in which a contact to the body of the finFET is formed on a first side of the fin and the second side of the fin is gated through a thin dielectric by a gate conductor. The gate conductor contacts the body on the first side of the fin, providing a dynamic Vt device. For this structure to work properly, shorting between the body contact and the source-drain diffusions must be avoided. For this to occur, the source-drain diffusions must be confined to close to the second sidewall surface of the fin. Due to the extremely narrow width of the fin, shorting between body contact and source-drain diffusions is virtually assured to occur. If the width of the fin is increased to prevent the source-drain diffusions from approaching the second (body contact) side of the fin, many of the desirable attributes of the finFET would be seriously degraded.
In view of the above, there is a need to provide a finFET formed on an insulating substrate, whereby a body contact is provided in such a way that does not degrade the desirable attributes of the finFET.